1. Field of the Invention
The present invention relates to programmable logic devices, and more particularly to a synchronous type programmable logic device which performs precharge of product term lines and sum term lines, decision and evaluation of outputs of the product term lines and the sum term lines synchronizing with clock signals from the outside.
2. Description of the Background Art
In recent years, in order to facilitate design and high integration of logic circuits, logic devices called a programmable logic array (PLA) and a programmable logic device (PLD) are widely used. The programmable logic device utilizes the fact that the combination logic can be expressed by product-sum type logics, and is provided with AND-plane which outputs the logical products of any input signals among a plurality of input signals to the product term lines, and with OR-plane which takes the logical sum of outputs of any product term lines among the product term lines of the AND-plane.
Both the AND-plane and the OR-plane have transistor arrays in similar manner to the read only memory (ROM), and the transistor array pattern is programmed, whereby prescribed logic function can be obtained. The program of logic realized by the programmable logic device is performed with presence/absence of a transistor or presence/absence of connection to transistors arranged in array form corresponding to the logic "1" or "0".
As one of such programmable logic device, there is a synchronous type programmable logic device applying the logic operation processing to input signals in response to an external clock.
FIG. 1 is a diagram showing an example of programmable logic devices in the prior art disclosed, for example, in Tomizawa et al. translation supervision, "Principles of CMOSVLSI DESIGN A Systems Perspective" page 332, published in 1988 by Maruzen Co., Ltd.
Referring to FIG. 1, the programmable logic device comprises an AND-plane 2a applying the logic product operation to inputs from an input buffer 1 for outputting, an OR-plane 4a receiving the logic product (product term line) outputs A1 through A4 from the AND-plane 2a and applying the logic sum operation processing thereto, and an output buffer 6 for latching the logic sum (sum term line) outputs 01-04 from the OR-plane 4a for outputting. In the constitution shown in FIG. 1, constitution of logic circuit of two inputs and four outputs is shown as an example.
The input buffer 1 comprises an input buffer circuit 1a receiving input signals IN1 from an outside and generating non-inverted signals and inverted signals, and an input buffer circuit 1b receiving input signals IN2 supplied from the outside and deriving non-inverted signals and inverted signals. The input buffer circuit 1a comprises an inverter IV10 receiving the input signals IN1 and transmitting the inverted signals to a complementary internal data input line B1, and an inverter IV11 receiving outputs of the inverter IV10 and transmitting the inverted signal to an internal data input line B1. The input buffer circuit 1b comprises an inverter IV20 receiving input signals IN2 from the outside and transmitting the inverted signal to a complementary internal data input line B12, and an inverter IV21 receiving outputs of the inverter IV20 and transmitting the inverted signal onto an internal data input line B2.
The AND-plane 2a comprises product term lines A1, A2 A3 and A4 arranged in directions orthogonal to the data input lines B1, B1, B2, B2, and transistor elements T21-T27 arranged selectively to the intersection points between the data input lines B1, B1, B2, B2 and the product term lines (data output lines) A1 to A4.
Potential supply lines D21-D24 for transmitting the reference potential in parallel to each of the potential term lines A1-A4. Each of the transistor elements T21-T27 comprises an insulation gate type field effect transistor, and is rendered conductive in response to the signal potential on the associated input signal line so as to connect the corresponding product term line and the corresponding potential supply line (D2i; i=1-4).
The OR-plane 4a have the product term lines A1-A4 from the AND-plane 2a arranged extending to its inside to receive the signal potentials on the product term lines A1-A4 as its input signals. The OR-plane 4a is further have, arranged to the direction intersecting the product term lines A1-A4, sum term lines 01-04 for taking the logical sum of any signal potentials on the product term lines A1-A4 and outputting it, and have transistor elements T41-T46 arranged selectively on the intersections between the product term lines A1-A4 and the sum term lines 01-04. Second potential supply lines D41-D44 are installed so as to transmit a reference potential (ground potential) in parallel to the sum term lines 01-04. Each of the transistor elements D41-D46 is rendered conductive in response to the signal potential on the corresponding product term line Ai (i=1-4) so as to connect the corresponding sum term line 0j (j =1-4) to the second potential supply line D4j.
An output buffer 6 is provided corresponding to each of the sum term lines 01-04, and comprises output circuits 6a-6d for latching the signal potential on the corresponding sum term line 0i and outputting it. Each of the output buffer circuits 6a-6d comprises a latch circuit Li for latching or passing the signal potential on the corresponding sum term line 0i in response to a clock signal CLK2 from the outside, and an inverter IV for inverting the output of the latch circuit Li and outputting the output data OUTi. That is, the output buffer circuit 6a comprises a latch circuit L1 for latching or passing the signal potential on the sum term line 01 in response to the clock signal CLK2, and an inverter IV30 for inverting the output of the latch circuit L1 and outputting an output data OUT1. The output buffer circuit 6b comprises a latch circuit L2 for latching the signal potential on the sum term line 02 in response to the clock signal CLK2, and an inverter IV40 for inverting the output of the latch circuit L2 and deriving an output data OUT2. The output buffer circuit 6c comprises a latch circuit L3 for latching the signal potential on the sum term line 03 in response to the clock signal CLK2, and an inverter IV50 for inverting an output of the latch circuit L3 and deriving an output signal OUT3. The output buffer circuit 6d comprises a latch circuit L4 for latching the signal potential on the sum term line 04 in response to the clock signal CLK2, and an inverter IV60 for inverting the output of the latch circuit L4 and deriving an output signal OUT4.
In order to precharge the product term line Ai of the AND-plane 2a to a prescribed potential, a precharge circuit 3a is installed. The precharge circuit 3a comprises p-channel MIS (insulation gate type filed effect) transistors PT21-PT24 for receiving the clock signal CLK1 supplied from the outside through the inverter IV1 at its gate and precharging each of the product term potential Vdd), and n-channel MIS transistors NT21-NT24 being rendered conductive in response to the inverted clock signal from the inverter IV1 and connecting each of the potential supply lines D21-D24 to the second reference potential (ground potential) Vss.
In order to precharge each of the sum term lines 01-04 of the OR-plane 4a to a precharge potential, a second precharge circuit 5a is installed. The precharge circuit a comprises p-channel MIS transistors PT51-PT54 being rendered conductive in response to the clock signal CLKOR the reference potential Vdd, and n-channel MIS transistors NT51-NT54 being rendered conductive in response to the clock signal CLKOR and precharging each of the potential supply lines D41-D44 to the ground potential Vss.
In order to generate the clock signal CLKOR controlling the operation timing of the precharge circuit 5a, a dummy AND circuit 7a is installed. The dummy AND circuit 7a comprises a dummy product term line AD and a reference potential supply line D70, transistor elements T73, T74, T75 and T76 arranged on the intersections between the dummy product term line AD and the internal data input lines B1, B1, B2, B2, p-channel MIS transistor PT71 precharging the dummy product term line AD to the power source potential Vdd in response to the inverted clock signal CLK1 from the inverter IV1, and n-channel MIS transistor NT72 being rendered conductive in response to the inverted clock signal CLK1 and coupling the potential supply line D70 with the ground Vss.
The number of the transistors connected to the dummy product term line AD of the dummy AND circuit 7a is equal to the maximum number among the number that the transistors connected to the product term lines A1-A4 can be turned on simultaneously. That is, since the non-inverted signal and the inverted- signal are derived from the input buffer circuits 1a, 1b respectively in the constitution shown in FIG. 1, the number of the transistors capable of being connected to one product term line becomes four at most. Consequently, four transistor elements are connected to the dummy product term line AD. The output AD of the dummy AND circuit 7a is used as the clock signal CLKOR controlling the precharge operation of the precharge circuit 5a through the inverter 8a.
The precharge circuit 3a and the AND-plane 2a constitute a synchronous type NOR circuit using the input signals IN1, IN2 supplied to the input buffer 1 as input, in accordance with the arrangement of the transistor elements T21-T27. Also the OR-plane 4a and the precharge circuit 5a constitute a synchronous type NOR circuit using the signal potentials on the product term lines A1-A4 from the AND-plane 2a as input, in accordance with the arrangement of the transistor elements T41-T46. Next, the operation will be described referring to FIG. 2 being its operation waveform diagram.
In the arrangement of AND plane 2a and OR plane 4a of FIG. 1, the following logical operations are performed, where a signal line and a signal thereon have the same characters denoted: EQU A1=IN1+IN2, EQU A2=IN1+IN2, EQU A3=IN1+IN2, EQU A4=IN1=IN2, EQU 01=A1, EQU 02=A1+A2+A3 EQU 03=A2, EQU 04=A4.
The clock signal CLK1 and the clock signal CLK2 do not become "H" simultaneously and do not overlap with each other, and constitute the non-overlapping two-phase clocks. When the clock signal CLK1 is at "H", the inverted clock signal CLK1 from the inverter IV1 becomes "L". Therefore the p-channel MIS transistors (hereinafter referred to simply as "pMIS transistors") PT21-PT24 included in the precharge circuit 3a are turned on, while the n-channel MIS (hereinafter referred to as "nMIS") transistors NT21-NT24 are turned off.
In this case, the AND synchronous type NOR circuit constituted by the AND-plane 2a and the precharge circuit 3a is at the precharge period. That is, the potential level of the product term line (hereinafter referred to as "output signal line") Ai (i=1-4) is "H" irrespective of input signals supplied to the input buffer 1. Also in the dummy AND circuit 7a, the pMIS transistor PT71 is turned on and the nMIS transistor NT72 is turned off, and the signal potential AD on the output signal line AD (hereinafter, a signal line and a signal transmitted onto that signal line are designated by the same reference numeral) is at "H".
On the other hand, in the OR-plane, the clock signal CLKOR being output of the inverter 8a is at "L", and the pMIS transistors PT51-PT54 included in the precharge circuit 5a are turned on and the nMIS transistors NT51 circuit NT54 are turned off. Consequently, the synchronous type NOR circuit constituted by the OR-plane 4a and the precharge circuit 5a is also at the precharge period, and each output signal (sum term line) 0i (i=1-4) is at "H" level.
Since the clock signal CLK2 is at the reverse phase with respect to the clock signal CLK1, the clock signal CLK2 is at "L" then. The latch circuits L1-L4 included in the output buffer 6 are at the data holding state in response to the clock signal CLK2 at "L", and latch the output signal 0i in the preceding cycle. Consequently, the output signal OUTi (i=1-4) of the preceding cycle is continuously held and outputted from the output buffer 6.
Next, operation will be described when the clock signal CLK1 changes from "H" to "L". The inverted clock signal CLK1 from the inverter IV1 rises from "L" to "H", and the AND synchronous type NOR circuit constituted by the AND-plane 2a and the precharge circuit 3a and the dummy AND circuit 7a are brought into the evaluation state. That is, in the precharge circuit 3a, the pMIS transistors PT21-PT24 are turned off and the nMIS transistors NT21-NT24 are turned on. Thereby the potential supply lines D21-D24 are connected to the ground potential Vss. Also in the dummy AND circuit 7a, the pMIS transistor PT71 is turned off and the nMIS transistor NT72 is turned on. Thereby the potential line D70 is connected to the ground potential Vss.
As a result, in the AND-plane 2a, among the transistors T21-T27 arranged on the lattice points between the data input lines B1, B1, B2, B2 and the data output lines (product term lines) A1-A4, if a transistor exists having the potential of "H" transmitted to its gate, the potential of the output line Aj to which that transistor is connected, is discharged through the transistor at the conductive state and falls from "H" to "L" level.
In the AND-plane 2a, the output line Aj to which is connected only a transistor element having no signal of "H" transmitted to its gate, maintains the "H" level of the high impedance state.
For example, in the waveform diagram shown in FIG. 2, assume that the input signal IN1 is at "L" and the input signal IN2 is at "H". In this case, transistor elements at the ON-state are the transistor elements T21, T23, T26 and T27. Consequently, the output signal line A3 maintains the "H" level of the high impedance state, and the output signal lines A1, A2 and A4 are discharged through the transistor elements at the ON-state and their potential falls to the "L" level.
Then the transistors at the ON-state connected to the output signal line A2 are two in number, and the transistor at the ON-state connected to the output signal lines A1, A4 is one in number. Since the speed at which the potential level of the output signal line Ai changes from "H" to "L" is nearly inversely proportional to the number of the transistors at the ON-state connected thereto, the discharge is rapid in the output signal line A2 to which the two transistor elements at the ON-state are connected, and the discharge is slow in the output signal lines A1, A4 to which one transistor element at the ON-state is connected.
The dummy AND circuit 7a uses any input signals from the input buffer 1 as its input, and the transistor element is provided corresponding to each input signal line. Therefore the transistor elements having the same number of the inputs (two transistors in FIG. 1) are always turned on. More specifically stated, the situation will be as follows. In the dummy AND circuit 7a, the transistors T73 and T74 turn on complementarily and the transistors T75 and T76 turn on complementarily. Therefore, two transistors always turn on in operation. In the AND plane 2a, at most two transistors turn on in operation with respect to a single output line Ai, because a single output line Ai can not be provided with three transistors in the arrangement shown in FIG. 1. Consequently, the output signal line AD is discharged to "L" at the speed equal to or higher than the highest one of the discharge speed in the output signal line Ai.
In response to the potential transition of the signal AD on the dummy logic output signal line AD, the potential level of the clock signal CLKOR from the inverter 8a varies from "L" to "H". In response to the clock signal CLKOR, the precharge operation of the precharge circuit 5a is finished, and the OR synchronous type NOR circuit constituted by the OR-plane 4a and the precharge circuit 5a is brought into the evaluation state.
That is, since the pMIS transistors PT51-PT54 included in the precharge circuit 5a are turned off and the nMIS transistors NT51-NT54 are turned on, the potential supply lines D41-D44 are connected to the ground potential Vss and the output signal lines 01-04 are separated from the power source potential Vdd. In the OR-plane 4a, among the transistor elements T41-T46 arranged on the lattice points corresponding to the intersection points between the output signal lines (product term lines) A1-A4 from the AND-plane 2a and the output signal lines (sum term lines) 01-04 of the OR-plane 4a, a transistor element having the potential of "H" transmitted to its gate is turned on. Consequently, in the OR-plane 4a, the potential of the sum term line 0j connected to the transistor element at the ON-state is changed from "H" to "L". The sum term line 0j to which such transistor element at the ON-state is not connected, remains at the high impedance state of "H".
As seen in the operation waveform diagram shown in FIG. 2, when only the product term line A3 is at "H" level and the level of the product term lines A1, A2 and A4 is "L", in the OR-plane 4a, only the transistor element 42 is turned on and any remaining element is turned off. Consequently, the potential of the sum term line 02 varies from "H" to "L". Then, since the potential transition speed of the product term lines A1 and A4 is slow as shown in FIG. 2, in the transition period that the clock signal CLKOR rises from "L" to "H" and the product term lines A1 and A4 are discharged from "H" to "L", the overlap period is produced at the intermediate voltage between "H" and "L". That is, in response to rise of the clock signal CLKOR, the period is produced in which the nMIS transistor is turned on in the precharge circuit 5a and the transistor element to be turned off in the OR-plane 4a still keeps the ON-state. Consequently in the overlap period, the potential is discharged and lowered through the transistors at the ON-state (transistor elements T41, T46 in FIG. 1). That is, as shown by arrow A in FIG. 2, since the discharge speed of the product term lines A1, A4 is slow, the signal potential on the sum term line 01, 04 is slightly lowered to a certain intermediate voltage.
On the other hand, if the clock signal CLK1 falls to the "L" level, the clock signal CLK2 at the reverse phase thereof rises to the "H" level. In response to this, the latch circuits L1-L4 included in the output buffer 6 become the through state where the signal supplied to the input portion is transmitted as it is to the output portion. Consequently, in response to rise of the clock signal CLK2 to "H", the output signal OUTi from the output buffer circuits 6a-6d receives the precharge voltage of the sum term line 0i and once becomes the "L" level. Then the output signal OUTi also varies in response to the potential variation of the sum term lines 01-04. Then, the intermediate voltage of the sum term lines 01, 04 held to intermediate voltage is higher than the input logic threshold voltage of the output buffer 6 (logic threshold voltage of the latch circuits L1-L4) and therefore is deemed as "H".
According to the above-mentioned operation, the output signal OUTi through the prescribed logic operation processing to the input signal INi is outputted from the output buffer 6. Relation between the input signal INi and the output signal OUTi depends on the program state, i.e., the arrangement of the transistor elements arrayed in the AND-plane 2a and the OR-plane 4a.
If the clock signal CLK2 falls to the "L" level, each of the latch circuits L1-L4 included in the output buffer 6 latches the supplied signal and outputs it continuously.
In the constitution of the above-mentioned example of prior art, the correspondence between the input signal INi and the output signal OUTi is as follows. EQU 01=OUT1=IN1.multidot.IN2 EQU 02=OUT2=IN1.multidot.IN2 EQU 03=OUT3=IN1.multidot.IN2 EQU 04=OUT4=IN1
Next, if the clock signal CLK1 is changed from "L" to "H", the synchronous type NOR circuit constituted by the AND-plane 2a and the precharge circuit 3a and the dummy AND circuit 7a first become the precharge state. In response to the transition of the dummy AND circuit 7a to the precharge state, the clock signal CLKOR from the inverter 8a varies from "H" to "L", and the synchronous type NOR circuit constituted by the OR-plane and the precharge circuit 5a becomes the precharge state. Thereby, except for data latched in the latch circuits L1-L4 included in the output buffer 6, the logic device is returned to the initial state.
The programmable logic device in the prior art is constituted as above described, and performs control of the precharge/evaluation operation using output signals from the dummy AND circuit. Consequently, after starting the evaluation of the AND-plane, the OR-plane can be brought into the evaluation state.
The inverter 8a to derive the clock signal for controlling the operation of the OR-plane has a large drive ability enough to drive the transistors PT51-PT54 and NT51-NT54 of the precharge circuit 5a for the OR-plane, and the rise speed of the clock signal CLKOR is great. Consequently at the time of finishing the precharge operation of the precharge circuit 5a for the OR-plane always, the discharge of the product term line is not yet performed sufficiently, and the period is produced in which the transistor element to be turned off in the evaluation state maintains the ON-state. Consequently, the potential of the sum term line 0i to maintain the "H" level potential is lowered to the intermediate potential, and the danger is increased that the signal potential in error is detected and outputted in the output buffer.
The degree of potential reduction of the sum term line to the intermediate potential becomes large as the scale of the logic device becomes large. The reason is as follows. As the number of input signals increases, the difference between the minimum discharge speed of the product term line Ai and the variation speed of the output signal AD of the dummy AND circuit 7a becomes large. On the other hand, when the number of the output signals increases, the number of the precharge transistors of the precharge circuit 5a for the OR-plane also increases accordingly, and therefore the inverter buffer 8a having large drive ability is used and the change speed of the clock signal CLKOR significantly exceeds the potential change speed of the product term line Ai. That is, after finishing the precharge, longer time is required for the transistor to be turned off in the OR-plane to hold the ON-state during the high impedance state of the sum term line. Consequently, longer time is required for the potential of the sum term line at the high impedance state to be discharged through such a transistor.
In general, the output buffer is provided at its input stage with a CMOS (complementary insulated gate transistors) inverter connected between the reference potential Vdd and another reference potential Vss. According to the intermediate potential on such sum term line, both the pMIS transistor and the nMIS transistor are turned on, and a problem occurs that the current flows through the transistors and the power consumption increases.
Further, two clock signals, clock signal for controlling the operation of the AND-gate and the OR-plane and clock signal for controlling the latch operation in the output buffer, must be used. Consequently, a problem occurs that the wiring occupation area of the clock signals increases, and the two-phase clock signals not to overlap each other have an overlap portion in the high speed operation state, and thereby accurate logic operation cannot be performed and also the timing design of the two-phase clock signals becomes difficult.
Further problem exists that the potential supply line for discharge is provided corresponding to each of the product term line and the sum term line, whereby the signal wiring occupation area increases and the high integration of the logic device is significantly obstructed.
In the constitution that the precharge and the evaluation operation of the OR-plane are controlled using the dummy AND circuit output, one operation cycle time depends on the evaluation finishing time, i.e., the time required from establishing the potential on the sum term line until latch of the established potential by the output buffer. Since the margin must be estimated for this time, a problem exists that the precharge timing of the OR-plane cannot be set so rapidly and the implementation of the logic device with high speed is difficult.